Method and circuit for detecting data error

ABSTRACT

An error detecting circuit includes syndrome calculating circuits which calculates quotients S0&#39;, S1&#39;, S2&#39; and S3&#39; by division of syndromes. When all of the syndromes are &#34;0&#34;, an error zero is detected by an error zero detecting circuit, and a signal is outputted. A single error detecting circuit detects a single error when S0&#39;=S1&#39;=S2&#39;=S3&#39; NOTEQUAL 0, outputting a signal. At this time, a J-latch holds a counted value &#34;j&#34; of the counter which counts the number of the division as data indicative of an error position. Based upon data calculated by adding circuits and multiplying circuits, a double error detecting circuit detects that there are two or more errors through determination whether or not equations (S0&#39;+S1&#39;)(S2&#39;+S3&#39;)=S1&#39;+S2&#39;)2 and (S0&#39;+S2&#39;)(S2&#39;+S3&#39;)=(S1&#39;+S2&#39;)(S1&#39;+S3 &#39;) can be formed, outputting a detection signal when double errors occur. At this time, the J-latch and an i-latch hold counted values &#34;j&#34; and &#34;i&#34; as data indicative of error positions. By an error component calculating circuit, error components Ei and Ej are calculated by (S0&#39;+S1&#39;)/(1+ alpha i-j) and S0-Ei, respectively because a syndrome S0=Ei+Ej.

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to a method and circuit for detecting adata error. More specifically, the present invention relates to a dataerror detecting circuit incorporated in a signal processing circuitwhich is used in a compact disc (CD) player.

2. Description of the prior art

In a CD player, an 8-bit symbol is produced based upon data which isread from a disc in the form of an EFM signal such that music signaldata can be reproduced; however, there is possibility that a data erroroccurs in the symbol. Such a data error originates in a defect whichtakes place when pits are written on the disc, a defect due to a woundwhich takes place in handling the disc, or a defect due to fluctuationor disturbance of a mechanical characteristic of the player. Therefore,in the CD player, in order to detect and correct such a data error, asystem called a Cross Interleave Reed-Solomon Code (CIRC) is utilized.

For better understanding of the present invention, the system isdescribed in outline. First, in the case where the data is recorded onthe disc, right channel data and left channel data each including 16-bitmusic signal data of 6 in total are divided into 8-bit symbols, andtherefore, 24 symbols in total are produced. After selectively delayingand re-composing these symbols, parity data Q₀, Q₁, Q₂ l and Q₃ (eachbeing 8 bits) of C₂ are added to the symbols in accordance with aReed-Solomon Code method, becoming 28 symbols in total. The 28 symbolsare further delayed by a time period different from each other,respectively, and parity data P₀, P₁, P₂ and P₃ (each being 8 bits) ofC₁ are also added to the 28 symbols in accordance with the Reed-SolomonCode method, becoming 32 symbols in total. Then, the 32 symbols areselectively delayed and the parity data Q₀, Q₁, Q₂ and Q₃, and P₀, P₁,P₂ and P₃ are inverted such that the symbols become a group of data tobe written, and thereafter, such a group of data are modulated in a formof an EFM (Eight to Fourteen Modulation) and recorded on the disctogether with synchronization signals.

In reproducing the disc, the 8-bit symbols of 32 in total are producedfrom an EFM signal which is read from the disc, such symbols areconducted in the reverse process of the above described writing process.More specifically, the 32 symbols are selectively delayed and the paritydata Q₀, Q₁, Q₂ and Q₃, and P₀, P₁, P₂ and P₃ are inverted, andthereafter, the symbols are C₁ -decoded, becoming 28 symbols in total.In C₁ -decoding process, a syndrome is calculated based upon therespective symbols, and error detection and correction is made basedupon such a calculated syndrome in accordance with the Reed-Solomon Codemethod. Furthermore, the 28 symbols being C₁ -decoded are C₂ -decodedafter selectively delaying the same, becoming 24 symbols in total. Assimilar to the C₁ -decoding process, in the C₂ -decoding process, asyndrome is calculated based upon the respective symbols, and errordetection and correction is made based upon such a calculated syndromein accordance with the Reed-Solomon Code method. Then, the 24 symbolsafter C₂ -decoding process are re-composed and selectively delayed,being restored to the original music signal data.

In addition, the CD system which utilizes a Cross InterleaveReed-Solomon Code method has been well known, and therefore, a moredetailed description will be omitted here.

Conventionally, in the case where a data error is to be detected inaccordance with the Reed-Solomon Code method, syndromes are calculatedin accordance with the following equation (1). ##EQU1## where, α is aroot of a polynomial of degree eight as follows:

    F(X)=X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1

As a result of the above described calculation, if all of the syndromesS₀, S₁, S₂ and S₃ are "0", it is detected that no errors occur, that is,error zero.

On the other hand, in the case where a data error occurs in only thej-th data D_(j), such a data error can be detected by determiningwhether or not relationship set forth in the following can be formed:

    S.sub.1.sup.2 =S.sub.0 ·S.sub.2, S.sub.2.sup.2 =S.sub.1 ·S.sub.3

    S.sub.0 ≠0, S.sub.1 ≠0, S.sub.2 ≠=0, S.sub.3 ≠0

and, a position where the data error occurs (error position) can beevaluated by calculating S₁ /S₀ =α^(j) and a logarithm thereof.

Furthermore, in the case where data errors occur in the data D_(j) andD_(i), since the following equations can be formed, by evaluating j andi, it is possible to detect that data errors occur.

    α.sup.j +α.sup.i =(S.sub.1 ·S.sub.2 +S.sub.0 ·S.sub.3)/(S.sub.1.sup.2 +S.sub.0 ·S.sub.2)

    α.sup.i ·α.sup.j =(S.sub.2.sup.2 +S.sub.1 ·S.sub.3)/(S.sub.1.sup.2 +S.sub.0 ·S.sub.2)

    0≦j, i≦31, j≠i

Furthermore, in accordance with the following equation, error componentsE_(j) and E_(i) can be evaluated. ##EQU2##

As to data error detection and correction in the CD by means of theabove described Reed-Solomon Code method, more detail description wasmade in Japanese Patent Application Laid-open No. 77529/1985.

In a circuit in which the above described data error detection andcorrection can be performed, there were disadvantages that a ROM forconverting the data into a logarithm and a number of multiplying anddividing circuits become necessary, that especially, in detecting doubleerrors, since it is necessary to repeatedly execute multiplication anddivision, it takes a long time to detect data errors and to calculateerror positions, and that the number of timing signals necessary forcalculation becomes large.

SUMMARY OF THE INVENTION

Therefore, a principal object of the present invention is to provide anovel method and circuit for detecting a data error.

Another object of the present invention is to provide a method andcircuit for detecting a data error, wherein it is possible to reduce thenumber of timing signals necessary for calculation.

Another object of the present invention is to provide a method andcircuit for detecting a data error, wherein it is possible to reduce thenumber of components or elements.

Another object of the present invention is to provide a method andcircuit for detecting a data error, wherein a circuitry constructionbecomes simple.

The other object of the present invention is to provide a method andcircuit for detecting a data error, wherein error detecting speed canbecome fast.

A method for detecting a data error in accordance with the presentinvention comprising the following steps of: calculating syndromes S₀,S₁, S₂ and S₃ based upon a plurality of data including parity data;detecting that no errors occur when all of the syndromes S₀, S₁, S₂ andS₃ are "0"; when all of the syndromes S₀, S₁, S₂ and S₃ are not "0",repeating division of the syndromes S₀, S₁, S₂ and S₃ by 1, α, α² and α³(α is a root of a polynomial of degree eight); determining whether ornot quotients S₀ ', S₁ ', S₂ ' and S₃ ' satisfy the following equations(a), (b) and (c) at every timing when the division is executed;

    S.sub.0 '=S.sub.1 '=S.sub.2 '=S.sub.3 '≠0            (a)

    (S.sub.0 '+S.sub.1 ')(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ').sup.2 (b)

    (S.sub.0 '+S.sub.2 ')(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ')(S.sub.1 '+S.sub.3 ')                                              (c)

when it is determined that the equation (a) is formed, detecting that asingle error occurs and holding the number of times j of the division asdata indicative of an error position; and when it is determined that theequations (b) and (c) are formed by numbers of times j and i of thedivision, detecting that double errors occur and holding the numbers oftimes j and i of the division as data indicative of error positions.

Furthermore, a circuit for detecting a data error in accordance with thepresent invention comprises: a syndrome calculating means which receivesa plurality of data including parity data and calculates syndromes S₀,S₁, S₂ and S₃ and divides the syndromes S₀, S₁, S₂ and S₃ by 1, α, α²and α³ l (α is a root of a polynomial of degree eight); a counting meansfor counting the number of execution times of division in the syndromecalculating means; an adding means which receives outputs S₀ ', S₁ ', S₂' and S₃ ' of the syndrome calculating means and evaluates S₀ '+S₁ ', S₁'+S₂ ', S₂ '+S₃ ', S₀ '+S₂ ' and S₁ '+S₃ '; an error zero detectingmeans which detects that all of the syndromes S₀, S₁, S₂ and S₃ are "0"based upon outputs of the syndrome calculating means and outputs of theadding means; a single error detecting means which detects S₀ '=S₁ '=S₂'=S₃ '≠0; a multiplying means which receives the output of the addingmeans and evaluates (S₀ '+S₁ ')(S₂ '+S₃ '), (S₁ '+S₂ ')², (S₀ '+S₂ ')(S₂ '+S₃ ') and (S₁ ''S₂ ')(S.sub. 1 '+S₃ '); a double error detectingmeans which determines whether or not equations (S₀ '+S₁ ')(S₂ '+S₃')=(S₁ '+S₂ ')² and (S₀ '+S₂ ')(S₂ '+S₃ ')=(S₁ '+S₂ ')(S₁ '+S₃ ') can beformed based upon outputs of the multiplying means; a first holdingmeans which holds a counted value j of the counting means based upon adetection output of the single error detecting means and a firstdetection output of the double error detecting means; and a secondholding means which holds a counted value i of the counting means basedupon a second detection output of the double error detecting means.

In the above described means, the syndromes S₀, S₁, S₂ and S₃ can beevaluated in the syndrome calculating means in a manner that at everytiming when a symbol is sequentially applied, an operation wherein 1, α,α² and α³ are respectively multiplied by the symbol and a multiplicationresult is added to a succeeding symbol is repeated. Such evaluatedsyndromes S₀, S₁, S₂ and S₃ are divided by 1, α, α² and α³ insynchronous with a clock signal in the syndrome calculating means. Atthis time, it is possible to detect a single error by determining onlywhether or not quotients S₀ ',S₁ ', S₂ ' and S₃ ' of division are comeinto existence that S₀ '=S₁ ∝=S₂ '=S₃ '=0, and an error position can beevaluated as a counted value of the counting means which counts thenumber of times of the division. Furthermore, double errors can bedetected by the double error detecting means in the manner that anoperation wherein S₀ '+S₁ ', S₂ '+S₃ ', S.sub. 1 '+S₂ ' and S₁ '+S₂ 'are evaluated by adding the quotients S₀ ',S₁ ', S₂ ' and S₃ ' to eachother and (S₀ '+S₁ '), S₂ +S₃ ') and (S₁ '+S₂ ') are calculated by themultiplying means based upon the outputs of the adding means, and it isdetermined by the double error detecting means whether or not themultiplication results are equal to each other, and in the case wherethe multiplication results are equal to each other, S₀ '+S₂ ', S₂ '+S₃', S₁ '+S₂ ' and S₁ '+S₃ ' are evaluated by the adding means and (S₀'+S₂ ')(S₂ '+S₃ ') and (S₁ '+S₂ ')(S₁ '+S₃ ') are calculated by themultiplying means based upon the outputs, and it is determined whetheror not the multiplication results are equal to each other is performedat every timing when the division of the syndromes is made. In such anoperation, when two equations (S₀ '+S₁ ')(S₂ '+S₃ ')=(S₁ '+S₂ ')² and(S₀ '+S₂ ')(S₂ '+S₃ +)=(S₁ '+S₂ ')(S₁ '+S₃ ') are both formed and thenumbers of times of the division are twice as such j and i, it ispossible to detect that double errors occur and error positions can beobtained as counted values of the counting means.

Therefore, it is possible to simplify the circuits for executingmultiplication and addition, and the number of timing signals becomessmall.

In accordance with the present invention, since it is possible toperform error detection by means of the timing signals for reading thesymbols from the RAM and for calculating the syndromes and the timingsignals for dividing the syndromes S₀, S₁, S₂, S₃ by 1, α,α² and α³, thenumber of the timing signals necessary for calculation can be reduced.In addition, since it becomes unnecessary to provide a ROM for logarithmconverting which is utilized for directly making an operation of errordetection, there is an advantage that the circuitry construction becomessimple and the number of components or elements can be reduced.Furthermore, there is a further advantage that error detection speedbecomes fast.

These objects and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the embodiments of the present invention when taken inconjunction with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing one embodiment in accordance with thepresent invention.

FIG. 2 is a block diagram showing a specific construction of a syndromecalculating circuit as shown in FIG. 1.

FIGS. 3A to FIG. 3D are circuit diagrams respectively showingcalculating elements for α^(n) and 1/α^(n) as shown in FIG. 2.

FIG. 4 is a schematic diagram showing a construction of a multiplyingcircuit.

FIG. 5 is a circuit diagram showing a construction of an error componentcalculating circuit.

FIGS. 6A to 6H is a timing chart showing an operation of FIG. 1embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to a description of an embodiment, first, a description will bemade on data error detection in accordance with the present invention.In the case of error detection of C₁, syndromes S₀, S₁, S₂ and S₃ areevaluated or calculated from symbols in accordance with the abovedescribed equation (1); however, in the present invention, the equation(1) is changed as an equation (1') as follows; ##EQU3## In the equation(1'), suffixes added to characters D indicative of the symbols arechanged in reverse of that of the equation (1), and thus, a symbol D₃₁in the equation (1') is actually a symbol D₀. This means that actualsymbols are named as D₀, D₁, D₂ . . . D₃₁ in the order that the symbolsare read from the disc; however, in the present invention, the symbolsare named as D₃₁, D₃₀ . . . D₀ in the reverse order, and therefore,addresses therefor are assigned in the reverse order.

If there are no errors in the symbols D₃₁ -D₀, all of the syndromes S₀,S₁, S₂ and S₃ becomes "0". However, in the case where errors occur insymbols D_(i) and D_(j) (j≦i), the syndromes can be calculated inaccordance with a following equation (2). ##EQU4## where, each of E_(i)and E_(j) is an error component.

When such calculated syndromes S₀, S₁, S₂ and S₃ are respectivelydivided by 1, α, α² and α³ j times, the syndromes respectively become S₀', S₁ ', S₂ ' and S₃ ' represented by a following equation (3), ##EQU5##In accordance with the equation (3), following equations (4)-(8) can beevaluated.

    S.sub.0 '+S.sub.1 '≠E.sub.j (1+α.sup.i-j)      (4)

    S.sub.1 '+S.sub.2 '=α.sup.i-j E.sub.i (1+α.sup.i-j) (5)

    S.sub.2 '+S.sub.3 '=α.sup.2(i-j) E.sub.i (1+α.sup.i-j) (6)

    S.sub.0 '+S.sub.2 '=E.sub.i (1+α.sup.i-j).sup.2      (7)

    S.sub.1 '+S.sub.3 '=α.sup.(i-j) E.sub.i (1+α.sup.i-j).sup.2 (8)

Now, in the case of a single error, if i=j and E_(i) =0, a followingequation (9) can be obtained in accordance with the equations (4), (5),and (6).

    S.sub.0 '+S.sub.1 '=S.sub.1 '+S.sub.2 '=S.sub.2 '+S.sub.3 '≠0 (9)

    (S.sub.0 '=S.sub.1 '=S.sub.2 'S.sub.3 '=0)

Therefore, by determining whether or not the equation (9) can be formed,it is possible to detect a single error. An error position at this timecan be represented by the number of times j of the division of thesyndromes S₀, S₁, S₂ and S₃, and the error component E_(j) becomes avalue of the syndrome S₀.

On the other hand, in the case of double errors, following equations(10), (11) and (12) can be obtained in accordance with the equations (4)and (5), (5) and (6), and (7) and (8), respectively and followingequations (13) and (14) can be obtained in accordance with the equations(10), (11) and (12).

    (S.sub.1 '+S.sub.2 ')/(S.sub.0 '+S.sub.1 ')=α.sup.i-j (10)

    (S.sub.2 '+S.sub.3 ')/(S.sub.1 '+S.sub.2 ')=α.sup.i-j (11)

    (S.sub.1 '+S.sub.3 ')/(S.sub.0 '+S.sub.2 ')=α.sup.i-j (12)

    (S.sub.0 '+S.sub.1 ')/(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ').sup.2 (13)

    (S.sub.0 '+S.sub.2 ')/(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ')(S.sub.1 '+S.sub.3 ')                                              (14)

This means that the equations (13) and (14) can be formed when thenumbers of times of the division of the syndromes S₀, S₁, S₂ and S₃ by1, α, α² and α³ become j and i, whereby it is possible to detect thedouble errors and error positions j and i can be evaluated.

The error component E_(i) can be evaluated by a following equation (15)in accordance with the (4).

    E.sub.i =(S.sub.0 '+S.sub.1 ')/(1+α.sup.i-j)         (15)

In the equation (15), it is possible to change "1+α^(i-j) " into α^(x)in the Galois field, and therefore, by converting the same into α^(x) bymeans of an ROM addresses of which are assigned with values of i-j, andby dividing S₀ '+S₁ ' by α^(x), the error component E_(i) is evaluated.The error component E_(j) can be evaluated by an equation E_(j) =S₀-E_(i) because S₀ =E_(i) +E_(j).

One embodiment of an error detection circuit which is constructed inaccordance with the above described error detection method is shown inFIG. 1. In FIG. 1, a RAM 1 is a memory to which the symbols D₀ -D₃₁ (thesuffixes added to the characters D are representative of an actualaddressing order) which has been EFM-converted in each frame are writtenin a predetermined order by an address control circuit (not shown),which being read or written when error detection and correction of C₁and C₂ is to be performed or when the data is to be outputted for D/Aconverting, and which being connected to a data bus 2. Syndromecalculating circuits 3, 4, 5 and 6 are respectively connected to thedata bus 2, each of which receiving the symbols D₃₁ -D₀ (the suffixesadded to the characters D are representative of the reverse addressingorder of the actual addressing order, and hereinafter, such reverseaddresses are utilized) which are sequentially read from the RAM 1, andwhich making the calculation in accordance with the above describedequation (1') and evaluating S₀ ', S₁ ', S₂ ' and S₃ ' by dividingcalculated syndromes S₀, S₁, S₂ and S₃ by 1, α, α² and α³, respectively.In addition, the syndrome calculating circuits 3, 4, 5 and 6 areoperated in synchronous with a clock pulse SCLK which is produced by atiming signal SYRAM for reading the symbols D₃₁ -D₀ from the RAM 1 and atiming signal SYNDCL for executing the division, and change between anoperation for calculating the syndrome and an operation for executingthe division can be performed by a control signal SCONT.

Each of adding circuits 7, 8, 9 and 10 has two inputs to which 8-bitdata are respectively applied, which making addition of Modulo 2 byexecuting E-OR (Exclusive OR) of respective bits of the applied data.Outputs S₁ ' and S₂ ' of the syndrome calculating circuits 4 and 5 areapplied to the inputs of the adding circuit 7, and an output S₁ ' of thesyndrome calculating circuit 4 and an output of a selecting circuit(multiplexer MPX) 11 are applied to the inputs of the adding circuit 8.The multiplexer 11 receives outputs S₂ ' and S₃ ' of the syndromecalculating circuits 5 and 6 and selects any one of them. Therefore, theadding circuit 8 makes addition of S₁ '+S₂ ' or S₁ '+S₃ '. On the otherhand, the outputs S₂ ' and S₃ ' of the syndrome calculating circuits 5and 6 are applied to the inputs of the adding circuit 10, and an outputS₀ ' of the syndrome calculating circuit 3 and an output of a selectingcircuit (multiplexer MPX) 12 are applied to the inputs of the addingcircuit 10. The multiplexer 12 receives the outputs S₁ ' and S₂ ' of thesyndrome calculating circuits 4 and 5 and selects any one of them.Therefore, the adding circuit 10 makes addition of S₀ '+S₁ ' or S₀ '+S₂'.

An error zero detecting circuit 13 and a single error detecting circuit14 respectively receive outputs of the adding circuits 7, 9 and 10 andthe output S₀ ' of the syndrome calculating circuit 3 and detect anerror zero and a single error, respectively. More specifically, theerror zero detecting circuit 13 detects that the symbols D₃₁ -D₀ arecorrect and no errors occur therein based upon determination of S₀ =0and S₀ +S₁ =S₁ +S₂ =S₂ +S₃ at a timing when the syndromes S₀, S₁, S₂ andS₃ are calculated, and outputs a detection signal ZE. On the other hand,the single error detecting circuit 14 determines whether or not aquotients S₀ ≠0 and whether or not the equation (9) can be formed atevery timing when the calculated syndromes S₀, S₁, S₂ and S₃ are dividedby 1, α, α² and α³ in the syndrome calculating circuits 3, 4, 5 and 6,and detects that a single error occurs in the symbols when S₀ '=0 andthe equation (9) is formed, and outputs a detection output 1E.

A multiplying circuit 15 multiplies the 8-bit outputs from the addingcircuits 7 and 8, and outputs a multiplied output (S₁ '+S₂ ')², that is,a right term of the equation (13) when the multiplexer 12 selects S₂ 'and a multiplied output (S₁ '+S₂ ')(S₁ '+S₃ '), that is, a right term ofthe equation (14) when the multiplexer 11 selects the output S₃ '. Onthe other hand, the multiplying circuit 16 multiplies the 8-bit outputsfrom the adding circuits 9 and 10, and outputs a multiplied output (S₂'+S₃ ')(S₀ '+S₁ '), that is, a left term of the equation (13) when themultiplexer 12 selects S₁ ' and a multiplied output (S₂ '+S₃ ')(S₀ '+S₂'), that is, a left term of the equation (14) when the multiplexer 12selects S₂ '. The outputs of the multiplying circuits 15 and 16 areapplied to a double error detecting circuit 17.

The double error detecting circuit 17 determines whether or not the8-bit outputs of the multiplying circuits 15 and 16 are coincident witheach other by making E-OR of the respective bits thereof. The doubleerror detecting circuit 17 outputs an inhibit signal INH for stoppingthe division in the syndrome calculating circuits 3, 4, 5 and 6 whensuch coincidence is detected, and further outputs a control signal MCONTfor controlling the multiplexers 11 and 12.

More specifically, the multiplexers 11 and 12 respectively select theoutputs S₂ ' and S₁ ' until the control signal MCONT is outputted, andtherefore, the double error detecting circuit 17 first determineswhether or not the equation (13) can be formed, and when it is detectedthat the equation (13) is formed, the outputs S₃ ' and S₂ ' arerespectively selected by the multiplexers 11 and 12 in response to thecontrol signal MCONT, and thereafter, the double error detecting circuit17 determines whether or not the equation (14) can be formed. Suchdetecting operation of the double error detecting circuit 17 is made atevery timing when the division by 1, α, α² and α³ is made in thesyndrome calculating circuits 3, 4, 5 and 6.

Furthermore, in the case where it is detected that the equations (13)and (14) are formed in the double error detecting circuit 17, this isstored in an internal flag and the double error detecting circuit 17outputs a control signal JDFC so as to stop outputting the controlsignal MCONT and the inhibit signal INH, thereafter, in order todetermine whether or not the equations (13) and (14) can be formed, thedouble error detecting circuit 17 makes the syndrome calculatingcircuits 3, 4, 5 and 6 continue the division. In addition, in the casewhere it is detected that the equations (13) and (14) are formed for thesecond time based upon the internal flag, the double error detectingcircuit 17 detects that two or more error occur in the symbols andoutputs a detection output 2E. In the case where it is detected for thethird time that the equations (13) and (14) are formed, the double errordetecting circuit 17 detects that there are errors which can not becorrected and outputs a signal COIN3.

On the other hand, the detection outputs ZE and 1E are applied to thedouble error detecting circuit 17 from the error zero detecting circuit13 and the single error detecting circuit 14, and when the detectionoutput ZE or 1E are generated, the double error detecting circuit 17outputs the inhibit signal INH so as to stop the succeeding division inthe syndrome calculating circuits 3, 4, 5 and 6.

A counting circuit 18 is a 6-bit counter which counts the number oftimes of the division by counting the clock pulse SCLK1 which makes thesyndrome calculating circuits 3, 4, 5 and 6 execute the division by 1,α² and α³. The lower 5 bits of an output of the counting circuit 18 areapplied to a J-latch 19 which is a first error position holding meansand an I-latch 20 which is a second error position holding means,respectively. The J-latch 19 is composed of 5 D-FFs, a latch operationof which is controlled by the detection output 1E of the single errordetecting circuit 14 and the output JDFC of the double error detectingcircuit 17. The J-latch 19 holds a counted value of the counting circuit18 as data indicative of an error position j when the detection output1E or JDFC is outputted. The I-latch 20 is composed of 5 DFFs, a latchoperation of which is controlled by the output 2E of the double errordetecting circuit 17. The I-latch 20 holds a counted value of thecounting circuit 18 as data indicative of an error position i when theoutput 2E is generated. The error positions j and i being held in theJ-latch 19 and the I-latch 20 are both inverted by inverters 21 and 22,being supplied the address control circuit (not shown) of the RAM 1through selection by a multiplexer 23. This means that the errorpositions j and i designates the address of the symbol in which an erroroccurs and the same are utilized for correcting the symbol. A reason whythe data of j and i are inverted by the inverters 21 and 22 is that theaddresses of the symbols D₀ -D₃₁ are to be put back in its actual orderbecause the same are assigned in the reverse order as described above.

In addition, an output Q₆ for the 6th bit of the counting circuit 18 isapplied to a correction impossibility detecting circuit 24. Thecorrection impossibility detecting circuit 24 detects that there are 3or more errors in the symbols and the same can not be correct, basedupon the detection outputs ZE, 1E, 2E and COIN3. More specifically, inthe case where both of the detection outputs ZE and 1E are not outputtedand the signal COIN3 is outputted, or in the case where the detectionoutputs ZE, 1E and 2E are not outputted when the output Q₆ of thecounting circuit 18 becomes "1" even though the division in the syndromecalculating circuits 3, 4, 5 and 6 are terminated 32 times or 28 times,the correction impossibility detecting circuit 24 outputs a detectionoutput NG indicative of impossibility of correction.

An i-j counter 25 is an i-j calculating means which evaluates differencei-j of the error positions necessary for calculating the error componentEi indicated in the equation (15), which being a 5-bit counter whichcounts the clock pulse SCLK1. A reset state of the i-j counter 25 isreleased by an inverted signal of an output 2EF1 of an internal flagwhich is set when the double error detecting circuit 17 detects for thefirst time that the equations (13) and (14) are formed. The i-j counter25 is stopped to count when the clock pulse SCLK1 is interrupted by thedetection output 2E which is outputted at the second detection.Therefore, in the case of the double errors, counting operation of thei-j counter 25 is started at the timing of the division for (j+1)th timeand stopped at the timing of the division for i-th time. Therefore, acounted value of the i-j counter 25 becomes i-j.

An S₀ '+S₁ ' register 26 is an S₀ '+S₁ ' holding means which is composedof 8 D-FFs, latch operation of which is performed by the output JDFCwhen the double error detecting circuit 17 detects for the first timethat the equations (13) and (14) are formed, whereby S₀ '+S₁ ' which isoutputted from the adding circuit 10 can be held in the S₀ '+S₁ 'register 26.

An error component calculating circuit 27 receives the outputs of the S₀∝+S₁ ' register 26 and the i-j counter 25, and calculates the errorcomponent E_(i) of the error position i based upon the equation (15). Inthe error component calculating circuit 27, a decoder system forconverting 1+α^(i-j) into α^(x) to make calculation simple.

An adding circuit 28 to which an output E_(i) of the error componentcalculating circuit 27 is applied evaluates a sum of Modulo 2 of S₀ 'which is a sum of the error components E_(i) and E_(j) and is equal tothe syndrome S₀ and the error component E_(i) calculated in the errorcomponent calculating circuit 27 such that error component E_(j) can beevaluated by E-OR for each bit.

Calculated error components E_(i) and E_(j) are applied to a multiplexer29, being selectively outputted by a control signal SEL which is thesame as that for the multiplexer 23. More specifically, when the errorposition data i is selectively outputted from the multiplexer 23, theerror component E_(i) is outputted from the multiplexer 29, and theerror component E_(j) is selected when the error position data j isselected.

An adding circuit 30 to which an output of the multiplexer 29 is appliedand a register 31 which is composed of D-FFs of 8 bits make errorcorrection. More specifically, the erroneous symbol D_(i) or D_(j) whichis read from the RAM 1 based upon the error position data i or j beingapplied to the address control circuit through selection of themultiplexer 23 is held in the register 31, and in the adding circuit 30,a sum of Modulo 2 of the erroneous symbol D_(i) or D_(j) and the errorcomponent E_(i) or E_(j) is made, and an addition result, that is, acorrected symbol is stored again in the same address of the RAM 1. Anoperation of the adding circuit 30 is controlled by a control signal ENAwhich is outputted from a correction control circuit 32, and no addingoperation is made in the cases of error zero and correctionimpossibility, and the adding operation is made in the cases of thesingle error and the double errors.

The above described error detection and correction circuit is a circuitwhich can be used for error detection and correction of the both of C₁and C₂. However, in the case of the error detection and correction ofC₂, since the number of symbols D₀ -D₂₇ becomes 28, the number oftimings when the syndromes S₀, S₁, S₂ and S₃ are calculated in thesyndrome calculating circuits 3, 4, 5 and 6 is 28, and the number oftimes of the division by 1, α² and α³ becomes 27. Therefore, in a timeperiod during when the error detection and correction of C₂ is to bemade, "4" is initially pre-set in the counting circuit 18. More detaildescription with respect to this point will be made later.

Next, description will be made on specific examples of major circuitsshown in FIG. 1.

FIG. 2 shows a circuit for implementing the syndrome calculatingcircuits 3, 4, 5 and 6, which includes E-OR gates 36 to each of whicheach of bits B₀ -B₇ of the symbol being sent on the data bus 2; 8 D-FFs37 to which outputs of the E-OR gates 36 are applied; α^(n) calculatingelement 38 and 1/α^(n) calculating element 39 to which outputs of theD-FFs 37 are respectively applied; and a multiplexer 40 which selectsoutputs of the calculating elements 38 and 39 and applies the samerespective inputs of the E-OR gates 36. D-FFs 37 are operated by theclock pulse SCLK1 which is produced by the above described timingsignals SYRAM and SYNDCL. The multiplexer 40 is controlled by thecontrol signal SCONT which change the calculation of the syndromes S₀,S₁, S₂ and S₃ and the division by 1, α, α² and α³. This means that incalculating the syndromes S₀, S₁, S₂ and S₃, the α^(n) calculatingelement 38 is used, and in calculating S₀ ', S₁ ', S₂ ' and S₃ ' throughthe division, the 1/α^(n) calculating element 39 is used.

Meanwhile, as seen from the equation (1'), in the syndrome calculatingcircuit 3, since the syndrome S₀ is a sum of the symbols D₃₁ -D₀ and S₀' is the quotient of the division S₀ by "1", the calculating elements 38is α⁰ and the calculating element 39 is 1/α⁰.

This means that in the case of the syndrome calculating circuit 3, thecalculating elements 38 and 39 and the multiplexer 40 are not needed,and the respective outputs Q₀ -Q₇ of the D-FFs 37 may be directlyapplied to the E-OR gates 36, respectively. Therefore, the symbol D₃₁which is read for the first time from the RAM 1 in synchronous with thetiming signal SYRAM for sequentially reading the symbols D₃₁ -D₀ isinputted to the D-FFs 37, and the symbol D₃₀ which is read for the nexttime is conducted to the addition of Modulo 2 with the outputs of theD-FFs 37, that is, D₃₁ in the E-OR gates 36, being held in the D-FFs 37.Such an operation is repeated 32 times from the timing when the D₃₁ isread to the timing when D₀ is read, and when the symbol D₀ is read, theoutputs of the D-FFs 37 becomes the syndrome S₀.

In addition, in the syndrome calculating circuit 4, the calculatingelement 38 is α and the calculating element 39 is 1/α. The α calculatingelement 38 has a circuit in which inputs I₀ 14 I₇ and outputs O₀ -O₇ areconnected to each other and 3 E-OR gates 41 are included, as shown inFIG. 3A. The 1/α calculating element 39 is a circuit in which inputs I₀-I₇ and outputs O₀ -O₇ are connected to each other and 3 E-OR gates 42are included, as shown in FIG. 3B. Therefore, in the syndromecalculating circuit 4, the symbol D₃₁ which is read for the first timefrom the RAM 1 in synchronous with the timing signal SYRAM and stored inthe D-FFs 37 is applied to the E-OR gates 36 as a multiplication resultof αD₃₁ by the α calculating element 38, and when the symbol D₃₀ isread, the addition of αD₃₁ +D₃₀ is made in the E-OR gates 36, and aresult thereof is stored in the D-FFs 37. By repeating such an operation32 times, the syndrome S₁ indicated in the equation (1') is calculatedand outputted from the outputs Q₀ -Q₇ of the D-FFs 37.

On the other hand, in the state where the 1/α calculating element 39 isselected and the inputs B₀ -B₇ of the E-OR gates 36 are made "0", atevery timing when the timing signal SYNDCL is applied once, the syndromeS₁ being held in the D-FFs 37 is divided as such 1/α by the 1/αcalculating element 39 and held in the D-FFs 37, and therefore, theoutputs Q₀ -Q₇ becomes S₁ '=S₁ /α. Therefore, by sequentially applyingthe timing signals SYNDCL of 31 in total, it is possible to calculate S₁' from S₁ /α to S₁ /α³¹.

Furthermore, the calculating element 38 of the syndrome calculatingcircuit 5 is α² and the calculating element 39 is 1/α². The α²calculating element 38 is an element having relationship of the inputsand the outputs as shown in FIG. 3C, such an element is obtainable byseries connection of 2 stages of the calculating elements shown in FIG.3A. On the other hand, the 1/α² calculating element 39 is an elementhaving relationship of the inputs and the outputs as shown in FIG. 3D,such an element is also obtained by series connection of 2 stages of the1/α calculating elements shown in FIG. 3B. In addition, the calculatingelement 38 of the syndrome calculating circuit 6 is α³ and thecalculating element 39 is 1/α³. The α³ calculating element is an elementin which 3 stages of FIG. 3A elements are connected in series, and the1/α³ calculating element is an element in which 3 stages of FIG. 3Belements are connected in series. In the syndrome calculating circuits 5and 6, the syndromes S₂ and S₃ indicated in the equation (1') arecalculated in synchronous with the timing signal SYRAM, and thecalculating of the equation (3) is made in synchronous with the timingsignal SYNDCL, respectively, and thus, S₂ ' from 1/α² to 1/α⁵² and S₃ 'from 1/α³ to 1/α⁹³ can be calculated.

FIG. 4 shows a schematic diagram of a circuit for constructing themultiplying circuits 15 and 16 as shown in FIG. 1. The data which ishandled in the Reed-Solomon Code method is the data of the Galois field,and thus, multiplication of the data can be implemented only by an ANDgate and E-OR gate. In FIG. 4, A₀ -A₇ is 8-bit data which is applied toone input of the multiplying circuit and B₀ -B₇ is 8-bit data which isapplied to the other input of the multiplying circuit. In addition, thereference numeral 44 denotes an AND gate, the reference numeral 45denotes a composite gate which is constructed by an AND gate and an E-ORgate, and the reference numeral 46 denotes an E-OR gate. Respective bitsof the data A₀ -A₇ and the data B₀ -B₇ are supplied to the AND gates 44and the composite gates 45 which are arranged in a matrix fashion, andrespectively applied to 2 inputs of the AND gates 44 and the 2 inputs ofthe AND gates within the composite gates 45. Therefore, by the AND gates44 and the AND gates within the composite gates 45, as in normalarithmetic calculation, logical products of respective bits of the dataA₀ -A₇ and the data B₀ -B₇ can be obtained. In order to obtain the sumof Modulo 2 of the logical product outputs for each bit, outputs of theAND gates within the composite gates 45 are applied to respective oneinput of the E-OR gates within the composite gates 45, and to respectiveanother input thereof, the outputs of the AND gates 44 of the pre-stageor the outputs of the composite gates 45 are applied. In addition, eachof the E-OR gates 46 selects upper 7 bits of each 15-bit output of thesum of Modulo 2 which is obtained by the AND gates 44 and the compositegates 45 and makes an operation of the sum of the Modulo 2 with theoutput of the lower 8 bits. More specifically, in the Galois field, theupper bits are represented as the selective sum of the lower bits. Forexample, the 9th bit is represented as the sum of Modulo 2 of the 1stbit, 3rd bit, 4th bit and 5th bit, and therefore, by arranging the E-ORgates 46 as shown in FIG. 4, the multiplication outputs X₀ -X₇ can beobtained. Thus, each of the multiplying circuits 15 and 16 can beconstructed by 64 AND gates and 77 E-OR gates without using a clockpulse, which outputs the multiplication result at every timing when thedata is inputted in a real time fashion.

FIG. 5 is a circuit diagram of the error component calculating circuit27 which includes a decoder 48 which receives a counted value of the i-jcounter 25 and outputs address signals a₁ -a₃₁ ; a ROM 49 which receivesthe address signals a₁ -a₃₁ ; and a selecting and adding circuits 50 ineach of which the 8-bit data of S₀ '+S₁ ' (in FIG. 5, referencecharacters A, B, C, . . . G, H are indicated from the least significantbit to the most significant bit) are selectively added in accordancewith an output of the ROM 49 so as to produce respective bits E_(i-0)-E_(i-7) (8 bits in total) of the error component E_(i). As describedabove, error component calculating circuit 27 is a means for calculatingthe equation (15), in this case, it is possible to convert 1+α^(i-j)into α^(x). The ROM 49 makes conversion from 1+α^(i-j) to α^(x) anddecides respective bit-constructions of the result in the case where the8-bit data is divided by α^(x). For example, in the case of i-j=1, 1+αis converted into α²⁵ and respective bits of the error component E_(i)which is obtained by division S₀ '+S₁ ' by α²⁵ can be represented asfollows; ##EQU6## Therefore, the selecting and adding circuits 50 whichproduce respective bits E_(i-7) -E_(i-0) select 8-bit data A-H of S₀'+S₁ ' based upon signals respectively outputted from the ROM 49 bymeans of AND gates 51 and make the addition of the Modulo 2 by means ofE-OR gates 52. Therefore, even though the division is not executedactually, only by applying the counted value of the i-j counter 25, theerror component E_(i) can be obtained in a real time fashion.

Next, an operation of the error detection and correction of C₁ and C₂which is performed by the circuit as shown in FIG. 1 will be brieflydescribed with reference to FIGS. 6A to 6H

As shown in FIGS. 6A to 6H, a processing period of 1 frame is composedof timings T₁ -T₆ and 49 timings t₀ -t₄₈ which constructs each of thetimings T₁ -T₆. Error detection and correction of C₁ is performed at thetimings T₁ -T₃ and the error detection and correction of C₂ is performedat the timings T₄ -T₆.

First, the syndrome calculating circuits 3, 4, 5 and 6 and the D-FFs ofeach portions, etc. are reset by a clear pulse SINT which is generatedat the timing t₀ of the timing T₁. The timing T₁ is a timing forsequentially reading 32 symbols D₃₁ -D₀ being stored in the RAM 1 andcalculating the syndromes S₀, S₁, S₂ and S₃, and the timing signalsSYRAM are arranged or distributed to be generated 32 in total within thetimings t₀ -t₄₈. Therefore, when the 32nd timing signal SYRAM isgenerated, calculation of the syndromes S₀, S₁, S₂ and S₃ is terminated.

Next, the timing T₂ is a timing for error detection, and the timingsignals SYNDCL are arranged or distributed to be generated 32 or more intotal within the timing T₂. In addition, by a clear pulse SINT which isgenerated at the timing t₀ of the timing T₂, an output of an AND gate 53as shown in FIG. 1 is generated and "0" is preset in the countingcircuit 18. Therefore, at every timing when the timing signal SYNDCL isgenerated, the counting circuit 18 is incremented and the division by 1,α, α² and α³ is executed once in the syndrome calculating circuits 3, 4,5 and 6, whereby a single error detection or double errors detection aremade based upon the result thereof. When all of the timing signalsSYNDCL are generated, in the case where there is a single error ordouble errors, one position of the error positions is latched in thej-latch 19 and the other position i is latched in the i-latch 20 and thedifference of the error positions is held in the i-j counter 25 and S₀'+S₁ ' is held in the register 26. Furthermore, a detection result of anerror zero, a single error, double errors or correction impossibility iscommunicated to the correction control circuit 32.

The timing T₃ is a timing for performing error correction, which isdivided by the control signal SEL into a timing when the error positioni is selected and the symbol D_(i) is read from the address and a timingwhen the symbol D_(i) being corrected by the adding circuit 30 iswritten in the same address of the RAM 1, and as similar thereto, atiming for reading the symbol D_(j) and a timing for writing the same ascorrected are formed.

In the case where the error detection and correction of C₂, the numberof symbols to be subjected to the error detection and correction becomes28 of D₂₇ -D₀. Therefore, during the timing T₄, there are 28 timingsignals SYRAM for reading the symbols D₂₇ -D₀ and calculating thesyndrome S₀, S₁, S₂ and S₃. By a clear pulse SINT which is generated atthe timing t₀ of the timing T₄, the data being held when error detectionor correction of C₁ is performed are all cleared, and therefore, insynchronous with 28 timing signals SYRAM, the syndrome S₀, S₁, S₂ and S₃of C₂ are obtained.

At the timing T₅, when a clear pulse SINT is generated at the timing t₀,an output is obtained from an AND gate 54 shown in FIG. 1 and "4" ispreset in the counting circuit 18.

Now, the reason why "4" is preset is described. As described above, inthe RAM 1, as shown in the following table, the addresses are assignedin the order where the symbols are read from the disc.

                  TABLE                                                           ______________________________________                                        Address  0      1      2    3    --   --   30   31                            Symbol   D.sub.0                                                                              D.sub.1                                                                              D.sub.2                                                                            D.sub.3                                                                            --   --   D.sub.30                                                                           D.sub.31                      Values of i, j                                                                         31     30     29   28   --   --   1    0                             ______________________________________                                    

However, as indicated in the equation (1), the indexes of α which ismultiplied into the symbols D₀ -D₃₁ are in the reverse order of theaddresses, and therefore, i and j which are evaluated by the circuit asshown in FIG. 1 becomes in the reverse order of the actual addresses.Therefore, as shown in FIG. 1, by inverting 5-bit binary data (2⁵ 32)indicative of i and j by means of the inverters 21 and 22, the actualaddresses can be obtained. However, in the case of error detection andcorrection of C₂, the symbols to be processed are the symbols stored inthe addresses 0-27, and therefore, possible values of i and j becomes0-27. Therefore, if each of the values of i and j is inverted as it is,the results are deviated from the actual addresses by "4", andtherefore, prior to inverting the same, "4" is to be added. This meansthat an adding circuit for adding "4" is needed; however, if "4" ispreset in advance in the counting circuit 18 which counts j, such asadding circuit is not needed, whereby the same circuit can be used inthe error detection and correction of C₁ or C₂.

After that "4" is preset in the counting circuit 18, the number oftiming signals SYNDCL generated for the timing T₅ becomes 28 or more,and thus, by the timing signals, the error detection of C₂ can be madein the similar manner in the above described timing T₂.

Then, at the timing T₆, in the same manner at the timing T₃, the errorcorrection of C₂ can be performed.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A method for detecting a data error, comprisingsteps of:calculating syndromes S₀, S₁, S₂ and S₃ based upon a pluralityof data including parity data; dividing the syndromes S₀, S₁, S₂ and S₃by 1, α, α² and α³ (α is a root of polynomial of degree eight) i timesor j times to produce quotients S₀ ', S₁ ', S₂ ' and S₃ '; andindicating an error position by said i or j when it is detected that thequotients S₀ ', S₁ ', S₂ ' and S₃ ' satisfy the following equations

    (S.sub.0 '+S.sub.1 ')(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ').sup.2

    (S.sub.0 '+S.sub.2 ')(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ')(S.sub.1 '+S.sub.3).


2. A method in accordance with claim 1, wherein said plurality of dataincluding parity data are data based upon Read-Solomon Code.
 3. A methodfor detecting a data error, comprising the following stepsof:calculating syndromes S₀, S₂ and S₃ based upon a plurality of dataincluding parity data; detecting that no errors occur when the syndromesS₀, S₂ and S₃ satisfy S₀ =S₁ =S₂ =S₃ =0; when S₀ =S₁ =S₂ =S₃ =0,repeating division of the syndromes S₀, S₁, S₂ and S₃ by 1, α, α² and α³a number of times j (α is a root of a polynomial of degrees eight) toproduce quotients S₁ ', s₁ ', s₂ ' and S₃ '; determining whether or notthe quotients S₀ ', S₁ ', S₂ ' and S₃ ' satisfy the following equations(a), (b) and (c) at every timing when the division is executed;

    S.sub.0 '=S.sub.1 '=S.sub.2 '=S.sub.3 '=0                  (a)

    (S.sub.0 '+S.sub.1 ') (S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ').sup.2 (b)

    (S.sub.0 '+S.sub.2 ') (S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.3 ') (c)

when it is determined that the equation (a) is formed, detecting thatthere is one erroneous data and holding the number of times j of thedivision as data indicative of an error position; when the equations (b)and (c) are formed, detecting that there are 2 or more erroneous dataand holding the number of times j of the division as data indicative ofan error position of one erroneous data; repeating the division by 1, α,α² and α³ a number of times i and determining whether or not thequotients S₀ ', S₁ ', S₂ ' and S₃ ' satisfy the equation (b) and (c) areformed, detecting that there are 2 erroneous data and holding the numberof times i as data indicative of an error position of the othererroneous data.
 4. A method in accordance with claim 3, wherein saidplurality of data including parity data are data based upon Reed-SolomonCode.
 5. A circuit for detecting a data error, comprising:a syndromecalculating means which receives a plurality of data including parietydata and calculates syndromes S₀, S₁, S₂ and S₃ and divides thesyndromes S₀, S₁, S₂ and S₃ by 1, α, α² and α³, (α is a root of apolynomial of degree eight) to produce outputs S₀ ', S₁ ', S₂ ' and S₃'; a counting means for counting the number of execution times ofdivision in the syndrome calculating means; an adding means whichreceives the outputs S₀ ', S₁ ', S₂ ' and S₃ ' of the syndromecalculating means and evaluates S₀ '+S₁ ', S₁ '+S₂ ', S₂ '+S₃ ', S₀ '+S₂' and S₁ '+S₃ '; an error zero detecting means which detects that all ofthe syndromes S₀, S₁, S₂ and S₃ are "0" based upon outputs of thesyndrome calculating means; a single error detecting means which detectsS₀ '=S₁ '=S₂ '=S₃ '=0; a multiplying means which receives the output ofthe adding means and evaluates (S₀ '+S₁ ')(S₂ '+S₃ '), (S₁ '+S₂ ')², (S₀'+S₂ ')(S₂ '+S₃ ') and (S₁ '+S₂ ')(S₁ '+S₃ '); a double error detectingmeans which determines whether or not equations (S₀ '+S₁ ')(S₂ '+S₃')=(S₁ '+S₂ ')² and (S₀ '+S₂ ')(S₂ '+S₃ ')=(S₁ '+S₂ ')(S₁ '+S₃ ') can beformed based upon outputs of the multiplying means; a first holdingmeans which holds a counted value j of the counting means based upon adetection output of the single error detecting means and a firstdetection output of the double error detecting means; and a secondholding means which holds a counted value i of the counting means basedupon a second detection output of the double error detecting means.
 6. Acircuit for detecting a data error, comprising:a syndrome calculatingmeans which receives a plurality of data including parity data andcalculates syndromes S₀, S₁, S₂ and S₃ and divides the syndrome S₀, S₁,S₂ and S₃ by 1, α, α² and α³ (α is a root of a polynomial of degreeeight) to produce outputs S₀ ', S₁ ', S₂ ' and S₃ '; a counting meansfor counting the number of execution times of division in the syndromecalculating means; an adding means which receives the outputs S₀ ', S₁', S₂ ' and S₃ ' of the syndrome calculating means and evaluates S₀ '+S₁', S₁ '+S₂ ', S₂ '+S₃ ', S₀ '+S₂ ' and S₁ '+S₃ '; an error zerodetecting means which detects that all of the syndromes S₀, S₁, S₂ andS₃ are "0" based upon outputs of the syndrome calculating means; asingle error detecting means which detects S₀ '=S₁ '=S₂ '=S₃ '≠0; amultiplying means which receives the output of the adding means andevaluates (S₀ '+S₁ ')(S₂ '+S₃ '), (S₁ '+S₂ ')², (S₀ '+S₂ ')(S₂ '+S₃ ')and (S₁ '+S₂ ')(S₂ '+S₃ '); a double error detecting means whichdetermines whether or not equations (S₀ '+S₁ ')(S₂ '+S₃ ')=(S₁ '+S₂ ')²and (S₀ '+S₂ ')(S₂ '+S₃ ')=(S₁ '+S₂ ')(S₁ '+S₃ ') can be formed basedupon outputs of the multiplying means; a first holding means which holdsa counted value j of the counting means based upon a detection output ofthe single error detecting means and a first detection output of thedouble error detecting means; a second holding means which holds acounted value i of the counting means based upon a second detectionoutput of the double error detecting means; an i-j calculating meanswhich evaluates difference of the counted values i and j; an S₀ '+S₁ 'holding means which holes an output S₀ '+S₁ ' of the adding means basedupon a first detection output of the double error detecting means; andan error component calculating means which calculates error component(S₀ '+S₁ ')/(1+α^(j-i)) based upon an output S₀ '+S₁ ' of the S₀ '+S₁ 'holding means and an output i-j of the i-j calculating means.
 7. Acircuit for detecting a data error, comprising:a syndrome calculatingmeans which receives a plurality of data including parity data andcalculates syndromes S₀, S₁, S₂ and S₃ and divides the syndromes S₀, S₁,S₂ and S₃ by 1, α, α² and α³ (α is a root of a polynomial of degreeeight) to produce outputs S₀ ', S₁ ', S₂ ' and S₃ '; a first addingmeans which receives the outputs S₁ ' and S₂ ' and provides S₁ '+S₂ '; afirst selecting means which receives the outputs S₂ ' and S₃ ' andselects any one of the output S₂ ' and S₃ '; a second adding means whichreceives the output S₁ ' and an output of the first selecting means andprovides S₁ '+S₂ ' or S₁ '+S₃ '; a third adding means which receives theoutputs S₂ ' and S₃ ' and forms outputs S₂ '+S₃ '; a second selectingmeans which receives the outputs S₁ ' and S₂ ' and selects any one ofthe outputs S₁ ', and S₂ '; a fourth adding means which receives theoutput S₀ ' and an output of the second selecting means and formsoutputs S₀ '+S₁ ' or S₀ '+S₂ ; a first multiplying means which receivesoutputs of the third and fourth adding means and outputs (S₁ '+S₂ ')² or(S₀ '+S₁ ')(S₂ '+S₃ '); a second multiplying means which receivesoutputs of the third and fourth adding means and outputs (S₀ '+S₁ ')(S₂'+S₃ ') or (S₀ '+S₂ ') (S₂ '+S₃ '); and a double error detecting meanswhich receives outputs of the first and second multiplying means anddetects that one of two equations (S₀ '+S₁ ') (S₂ '+S₃ ')=(S₁ '+S₂ ')²and (S₀ '+S₂ ') (S₂ '+S₃ ')=(S₁ '+S₂ ') (S₁ '+S₃ ') is formed bycontrolling the first and second means in response to a detection outputat a timing when the other of the two equations is formed.